In an electronic switching system, three main techniques, i.e., modularization technique, redundancy technique and duplication technique, are used in combination to improve operational reliability and extend functional performances, wherein a number of processors performing a variety of functions are involved therein and practical and useful cooperations among the processors are achieved by using an inter-processor communications (IPC) network.
In such an electronic switching system based on the IPC network, there are employed nodes at some intermediate points of the IPC network in order to route and arbitrate a data flow among processors.
Especially, in an asynchronous transfer mode (ATM) switching system, IPC data is transmitted in the unit of a data packet, i.e., a cell, through an ATM switching module. The data packet includes an information field and a header containing a node address and a payload type field that represents the type of inforamtion in the inforamtion field.
Referring to FIG. 1, there is depicted a schematic block diagram of two conventional IPC paths for two duplicated processors in an ATM switching system.
A first processor 10, a first node 20, a first controller 40, a first node switching block 30 and a first upper layer ATM switching module (not shown) are duplicated to make a second processor 50, a second node 60, a second controller 80, a second node switching block 70 and a second upper layer ATM switching module (not shown), respectively. All duplicated functional units including the upper layer ATM switching modules operate based on an active and stand-by mode scheme.
Each of the first and the second nodes is connected to its corresponding node switching block and controller, while the processors and the upper layer ATM switching modules are cross-linked to the nodes 20 and 60 and node switching blocks 30 and 70, respectively, wherein connections of the nodes except for the first node 20 and the second node 60 are not shown for the sake of simplicity.
In this case, the first functional units 10, 20, 30 and 40 are assumed to be in an active mode and the second functional units 50, 60, 70 and 80 are assumed to be in a stand-by mode.
The first node switching block 30 receives and transmits IPC data from and to an upper layer ATM switching module in the active mode. Operational details of the conventional node 20 will now be described with reference to FIGS. 1 and 2, wherein FIG. 2 depicts a detailed block diagram of the first node 20.
The IPC data from the first node switching block 30 is written to a receiving first-in-first-out (FIFO) buffer 120 on a cell-by-cell basis. The first controller 40 checks whether a complete data packet is written to the receiving FIFO buffer 120. When the complete data packet is written to the receiving FIFO buffer 120, the first controller 40 makes a lower link interface block 110 read the data packet in the receiving FIFO buffer 120 and send the IPC data packet to the first and the second processors 10 and 50.
The active first processor 10 receives the IPC data packet from the lower link interface block 110 and processes the IPC data packet received.
After processing the IPC data packet, the first processor 10 sends a processed IPC data packet (PIPCD) to the two duplicated nodes 20 and 60. Since the first node 20 is in the active mode, the first node 20 receives the PIPCD at the lower link interface block 110.
The lower link interface block 110 detects a busy terminal, i.e., a terminal coupled to the active processor 10, receives the PIPCD from the busy terminal and writes the PIPCD to a sending FIFO buffer 130.
When the complete data packet of the PIPCD written in the sending FIFO buffer 130 is checked by the first controller 40, the first controller 40 makes the first node switching block 30 receive the PIPCD from the first node 20 and send the PIPCD to the first and second upper layer ATM switching modules.
As described above, since such a node configuration described above provides only one path for the two duplicated processors to the upper layer ATM switching module, when the ATM switching system wants to improve or change the program in the processor to improve function thereof, there is no other path through which a new program can be received, i.e., no other path independent from a switching path through which the switching information is transmitted.
Until now, therefore, in order to change or improve the program in the processor, one of the following two conventional methods has usually been employed. In a first method, an operator first disconnects the path from the data processing block to the upper layer ATM switching module and then change or improve the program in the data processing block directly. In a second method, a new program, i.e., an improved or changed version of an old program, is transmitted to the active data processing block through the switching path in a same way as ordinary IPC data, and the active data processing block sends the new program to the stand-by data processing block through the duplication control path (not shown). When all the new program is received, the active and the stand-by modes of the functional blocks are switched, thereby the active mode block becoming a stand-by mode block and the stand-by mode block becoming an active mode block. The new program installed in the active mode block, which was in the stand-by mode previously, will be copied into the stand-by mode block, which was in the active mode before.
In the first method, it need stop the switching operation while new program is received. On the other hand, in the second method, the switching operation need not be stopped, but since the path is commonly used to switch the ordinary IPC data and to receive the new program data, the operation time of the switching function will be delayed and an overflow in the payload that causes a malfunction of the ATM switching system will be transmitted to the processor or the path.